This invention relates to a circuit arrangement for use in processing a fault or an error occurring in a control memory including in a data processing system.
A conventional circuit arrangement of the type described comprises an error detecting circuit and an error correcting circuit together with a control memory loaded with a plurality of microinstructions. The error detecting circuit is for detecting an error of each microinstruction read out of the control memory while the error correcting circuit is for correcting the error to obtain a correct microinstruction. With this structure, each microinstruction is always sent from the control memory through both of the error detecting circuit and the error correcting circuit even when an error is not detected by the error detecting circuit. Therefore, an increase of a machine cycle is inevitable.
In another conventional circuit arrangement, the error detection alone is normally carried out for each microinstruction read out of a control memory by the use of an error detection circuit. An error correction circuit is operated only when an error is detected by the error detection circuit. With this structure, it is possible to shorten the machine cycle as compared with the above-mentioned circuit arrangement.
In the last-mentioned conventional circuit arrangement, assume an irremediable hardware error occurs in a portion of the control memory which may be called an erroneous portion. The error correction circuit should correct an error of each microinstruction each time when the erroneous portion is accessed. Therefore, it takes a long time to process each microinstruction read out of the erroneous portion. This lengthens an average time of executing the microinstructions when the hardware error occurs in the control memory.
At any rate, both of the conventional circuit arrangements carry out not only error detection but also error correction on occurrence of an error. In order to enable the error correction, each microinstruction should be formed by an error correcting code. Although the error detection alone is simply possible by addition of one or more parity bits, such as error correcting code requires extra redundant bits greater in number than the parity bit or bits, as is well known in the art. Thus, use of the error correcting code results in the control memory of an increased bit capacity.
In U.S. Pat. No. 4,010,450 issued to Porter et al and assigned to Honeywell Information Systems, a computer system is disclosed which is operable even when a hardware error occurs in a main memory. More specifically, the computer system comprises first and second addressing paths for addressing first and second portions of the main memory. When a fault, such as the hardware error, is detected on addressing the first portion of the main memory through the first addressing path, the first addressing path is switched to the second addressing path. Thus, the main memory should have the first and the second portions which are individually accessed through the first and the second addressing paths, respectively. The main memory is therefore redundant in structure.
It is difficult to apply the computer system to a circuit arrangement for use in combination with a control memory because a small capacity is often required in the control memory.